1. Field of the Invention
The present invention relates to a manufacturing method of a bottom plate of a capacitor. More particularly, the present invention relates to a manufacturing method of a crown structure of a capacitor in dynamic random access memory (DRAM).
2. Description of Related Art
With the steady improvement in integrated circuit (IC) fabrication, the dimensions of IC devices are greatly reduced. With a higher packing density, data transfer rate of IC products is higher while its functions and scope of applications continues to expand. In order to sustain the necessary growth, miniaturization of device dimensions in an IC chip has always been one major target in the semiconductor industry. This can be seen in the recent transition of manufacturing technologies from the VLSI to ULSI regime.
At present, one of the major products of integrated circuits in dynamic random access memory (DRAM). With the demand for packing more devices into a given wafer chip, available surface area of a capacitor for forming each memory cell is correspondingly reduced. The reducing of the available surface area causes electric charges stored in the capacitor insufficient and also causes data accessing difficult. That is, the data stored in the capacitor is easily lost and affected by other external factors. The repeating data refreshing operations are necessary for data safe storage, which increases the cost of operating the devices. Therefore, a demand for higher capacitance in a limited area of the device is continuously developed for storing more data. A method for higher capacitance of a capacitor is using a stacked structure or a crown structure of the capacitor for more surface area.
FIGS. 1A-1G shows cross-sectional views of a conventional manufacturing method of a bottom plate of a capacitor in the DRAM. Referring to FIG. 1A, a metal oxide semiconductor (MOS) transistor 102 is formed in a substrate 100. The MOS transistor 102 comprises a gate 102a, a pair of source/drain regions 102b and a spacer 102c. Next, an insulation oxide layer 104 is deposited over the substrate 100, and then a photo resist layer 106 is formed over the insulation oxide layer 104, in which a portion of the insulation oxide layer 104 is covered by the photo resist layer 106.
Referring to FIG. 1B, the exposed portion of the insulation oxide layer 104 is then etched to form a capacitor node contact opening 108 therein. One of the source/drain regions 102b is then exposed, as shown in FIG. 1B. Next, the photo resist layer 106 is removed.
Referring to FIG. 1C, a first polysilicon layer (not shown) is deposited over the insulation oxide layer 104 by, for example, a method of low-pressure chemical vapor deposition. The contact opening 108 is then filled with the polysilicon. The resistance of the first polysilicon layer is changed to about 500 .mu..OMEGA..about.1200 .mu..OMEGA. by heavily doping with ions. Therefore, the first polysilicon layer can be conductive material for the capacitor. The first polysilicon layer above the insulation oxide layer 104 is eliminated by, for example, a method of chemical mechanical polishing or etching back and then a portion of the first polysilicon layer in the contact opening 108 is changed into a contact plug 108a.
Next, referring to FIG. 1D, a second polysilicon layer 110 is formed over the insulation oxide layer 104 by, for example, a method of low-pressure chemical vapor deposition. The second polysilicon layer 110 is then heavily doped with ions. A photo resist layer 112 with a predetermined pattern is formed over the second polysilicon layer 110, for example, the photo resist layer 112 has an opening 112a above the position of the plug 108a. The exposed portions of the second polysilicon layer 110 are etched to form some grooves therein, for example, a groove 114 above the contact plug 108a as shown in FIG. 1E. After that, referring to FIG. 1F, the second polysilicon layer 110 is etched and changed to a crown-like bottom plate 110b by a photolithography precess. The crown-like bottom plate 110b is connected to the contact plug 108.
The conventional manufacturing method of a polysilicon bottom plate is described above. After the formation of the bottom plate, material with a high dielectric constant such as tantalum pentoxide is then deposited over the formed structure, for forming the capacitor. However, the crown-like structure of the bottom plate easily results in the leakage phenomenon, which bring the bottom plate not effectively storing the charges, that is, the bottom can not work well to be a function of capacitance.
In light of the foregoing, there is a need to provide a bottom plate, which reduces the leakage phenomenon and possesses a reliable function of capacitance.